공동 패키지 광학 시장(2026-2036년)

The co-packaged optics (CPO) market addresses a structural bottleneck in AI datacentre infrastructure: as switch ASIC bandwidth doubles roughly every 18?24 months while the electrical reach of copper signalling shrinks at higher SerDes rates, conventional pluggable optical transceivers are reaching fundamental physical and economic limits. CPO resolves this by integrating the optical engine directly within the switch ASIC or GPU/XPU package, shortening the electrical path, cutting interconnect power consumption from roughly 15 picojoules per bit toward 5 pJ/bit and below, and removing the front-panel density ceiling that constrains pluggable designs at 102.4 Tbps and above.

The market comprises two sub-segments with distinct timing. Scale-out CPO ? optical engines for Ethernet and InfiniBand network switches ? is the earlier and more standardised segment, with first commercial deployments at hyperscalers in 2026 on Broadcom Tomahawk 6-based platforms. Scale-up CPO ? optical I/O integrated within GPU packages to replace copper interconnects such as NVLink ? begins its volume ramp later in the decade with the NVIDIA Rubin generation, and is widely expected to become the larger and faster-growing of the two sub-segments as GPU optical I/O attach rates rise.

Importantly, CPO is additive rather than a wholesale replacement for pluggable transceivers, which retain structural dominance in enterprise, telecom, and lower-bandwidth cloud applications throughout the forecast period. The late-2020s window is best understood as a managed coexistence of pluggable, near-package, and co-packaged optics across different datacentre tiers, with the balance shifting steadily toward integration as reliability, thermal, and interoperability challenges are resolved.

The competitive landscape spans vertically integrated leaders ? NVIDIA and Broadcom ? and a layer of specialist innovators. Among these, Ayar Labs is notable: the fabless optical I/O chiplet developer closed a $500 million Series E round in March 2026 led by Neuberger Berman, bringing total funding to approximately $870 million and a valuation of $3.75 billion, with strategic backing from AMD and NVIDIA. The proceeds are earmarked for scaling high-volume production and test capacity for its co-packaged optics solution. Advanced semiconductor packaging ? 2.5D interposers, through-silicon vias, fan-out, glass interposers, and 3D hybrid bonding ? is the critical enabling technology and the principal supply-chain bottleneck, alongside laser source capacity. NVIDIA's March 2026 investment in Lumentum and Coherent underscores how upstream silicon-photonics and laser supply have become strategically central to the CPO ecosystem.

The Global Co-Packaged Optics Market 2026-2036 delivers a comprehensive analysis of one of the most significant technological transitions in data centre infrastructure since the advent of optical communications. As switch ASIC bandwidth doubles roughly every 18?24 months while the electrical reach of copper signalling shrinks at higher SerDes rates, conventional pluggable optical transceivers are reaching fundamental physical and economic limits. Co-packaged optics (CPO) resolves this by integrating the optical engine directly within the switch ASIC or GPU/XPU package, dramatically shortening the electrical path, reducing interconnect power consumption from roughly 15 picojoules per bit toward 5 pJ/bit and below, and removing the front-panel density ceiling that constrains pluggable designs at 102.4 Tbps and above.

This report examines the market across two principal sub-segments. Scale-out CPO ? optical engines for Ethernet and InfiniBand network switches ? is the earlier and more standardised segment, with first commercial deployments at hyperscalers using Broadcom Tomahawk 6-based platforms. Scale-up CPO ? optical I/O integrated within GPU packages to replace copper interconnects such as NVLink ? ramps later in the decade with the NVIDIA Rubin generation and is expected to become the larger, faster-growing sub-segment as GPU optical I/O attach rates rise. CPO is positioned as additive rather than a wholesale replacement for pluggable transceivers, which retain structural dominance in enterprise, telecom, and lower-bandwidth cloud applications, producing a managed coexistence of pluggable, near-package, and co-packaged architectures across the forecast period.

The report provides detailed coverage of CPO technology fundamentals, photonic integrated circuits, optical engines, and the advanced semiconductor packaging that enables CPO ? including 2.5D silicon, organic and glass interposers, through-silicon vias, fan-out wafer-level packaging, and 3D hybrid bonding. It analyses EIC/PIC integration approaches, optical alignment and laser integration, CPO standards, the competitive divergence between NVIDIA's vertical integration and Broadcom's open-ecosystem strategy, supply-chain structure, regional dynamics, adoption-curve and scenario analysis, and ten-year market forecasts by application, component, technology generation, and packaging technology. Drawing on extensive primary research and industry interviews, it offers strategic intelligence for semiconductor professionals, investors, data centre operators, and technology strategists seeking to understand how CPO will reshape AI and data centre architecture through 2036.

Report Contents

• Executive summary, market definition, scope, and key drivers and restraints
• Modern high-performance AI data centre architecture, switches, and switch ASIC bandwidth scaling
• Optical transceiver trends, pluggable vs. CPO design decisions, and the optical engine
• Heterogeneous integration, interconnection techniques, and key CPO applications (network switch and computing optical I/O)
• EIC/PIC integration and 2D-to-3D integration options
• CPO + XPU/switch ASIC packaging structures and challenges
• NVIDIA vs. Broadcom strategic comparison and CPO product benchmark
• Current and future AI system architecture
• Ten-year market forecasts: units shipped and revenue for optical I/O and CPO network switches; total CPO market; forecasts by integration technology and packaging technology
• CPO industrial ecosystem and value-chain analysis
• Challenges and solutions for future AI systems: LLM growth, scale-up/scale-out/scale-across networks, SerDes bottlenecks, copper-to-optical migration, power efficiency and latency benchmarks
• Introduction to CPO: PICs, optical engines, optical power supplies, benefits, and standards
• Packaging for CPO: 2.5D silicon, organic and glass technologies; 3D advanced packaging; TSV, fan-out, hybrid bonding; optical alignment, fiber array units, and laser integration
• CPO market analysis: switch CPO, XPU optical I/O, pricing and cost, regional dynamics, TAM, market restraints, adoption curve, competitive landscape, and scenario analysis
• Global datacom market trends and market outlook for scale-out and scale-up
• High-density connectors, emerging supply-chain dynamics, and systems integrators
• Company profiles including Alphawave Semi, AMD, Amkor Technology, ASE Technology Holdings, Astera Labs, Avicena, AXT, Ayar Labs, Broadcom, CEA-Leti, Celestial AI, Cisco, Coherent, Corning, Credo, DenseLight, EFFECT Photonics, EVG, Fabrinet, FOCI (Fiber Optical Communication Inc.), FormFactor, Foxconn, Furukawa Electric, GlobalFoundries, Henkel, Hewlett Packard Enterprise, Hisense Broadband Multimedia Technologies, IBM, imec, Intel, JCET Group, Kyocera, Lightmatter, LioniX International, Lumentum, MACOM, Marvell, MediaTek, Molex, NVIDIA, OpenLight, POET Technologies and more....

Table of Contents

1 EXECUTIVE SUMMARY

• 1.1 Report Overview and Key Findings
• 1.2 Market Definition and Scope
  • 1.2.1 Definition of Co-Packaged Optics (CPO)
  • 1.2.2 Scope of This Report
• 1.3 Key Market Drivers and Restraints
• 1.4 Modern High-Performance AI Data Centre Architecture
  • 1.4.1 Physical Infrastructure Hierarchy
  • 1.4.2 Network Architecture
  • 1.4.3 Power and Cooling Considerations
• 1.5 Switches: Key Components in Modern Data Centres
  • 1.5.1 Switch Architecture Evolution
  • 1.5.2 Switch ASIC Technology
  • 1.5.3 Optical Transceiver Requirements
• 1.6 Advancements in Switch IC Bandwidth and the Need for CPO Technology
  • 1.6.1 Historical Bandwidth Scaling
  • 1.6.2 SerDes Technology Evolution
  • 1.6.3 Electrical Signalling Limits
  • 1.6.4 Front-Panel Density Constraints
  • 1.6.5 Power Consumption Trajectory
• 1.7 Overview of Key Challenges in Data Centre Architectures
  • 1.7.1 Thermal Management
  • 1.7.2 Power Delivery
  • 1.7.3 Cable Management
  • 1.7.4 Reliability and Serviceability
  • 1.7.5 Standards and Interoperability
• 1.8 Key Trend of Optical Transceivers in High-End Data Centres
  • 1.8.1 Historical Evolution
  • 1.8.2 Technology Migration Path
• 1.9 Design Decisions: CPO vs. Pluggables Comparison
  • 1.9.1 Performance Comparison
  • 1.9.2 Operational Comparison
  • 1.9.3 Economic Comparison
• 1.10 What is an Optical Engine (OE)?
  • 1.10.1 Functional Description
  • 1.10.2 Optical Engine Components
  • 1.10.3 Performance Parameters
• 1.11 Heterogeneous Integration and Co-Packaged Optics
  • 1.11.1 The Heterogeneous Integration Imperative
  • 1.11.2 Integration Approaches for CPO
  • 1.11.3 TSMC's Role in Heterogeneous Integration
• 1.15 Overview of Interconnection Techniques in Semiconductor Packaging
  • 1.15.1 Wire Bonding
  • 1.15.2 Flip-Chip Bumping
  • 1.15.3 Micro-Bumping
  • 1.15.4 Through-Silicon Via (TSV)
  • 1.15.5 Hybrid Bonding
  • 1.15.6 Redistribution Layer (RDL)
• 1.16 Key CPO Applications: Network Switch and Computing Optical I/O
  • 1.16.1 Scale-Out Network Switching
  • 1.16.2 Scale-Up Computing Optical I/O
• 1.17 EIC/PIC Integration by Advanced Interconnect Techniques
  • 1.17.1 Integration Requirements
• 1.18 2D to 3D EIC/PIC Integration Options
  • 1.18.1 2D Integration Architecture
  • 1.18.2 2.5D Integration Architecture
  • 1.18.3 3D Integration Architecture
• 1.19 Benchmark of Different Packaging Technologies for EIC/PIC
• 1.20 Examples of Packaging a 3D Optical Engine with an IC
  • 1.20.1 Configuration 1: EIC-on-PIC with Micro-Bumps
  • 1.20.2 Configuration 2: PIC-on-EIC with Through-Silicon Vias
  • 1.20.3 Configuration 3: 3D SoIC with Hybrid Bonding
• 1.21 Types of CPO + XPU/Switch ASIC Packaging Structures
  • 1.21.1 Type I: Optical Engines on Package Periphery
  • 1.21.2 Type II: Optical Engines Co-Located with ASIC on Interposer
  • 1.21.3 Type III: 3D Stacked Optical Engines
• 1.22 Challenges and Future Potential of CPO Technology
  • 1.22.1 Technical Challenges
  • 1.22.2 Commercial Challenges
    • 1.22.2.1 Future Potential
• 1.23 NVIDIA vs. Broadcom: Strategic Comparison in AI Infrastructure and CPO
  • 1.23.1 NVIDIA's CPO Strategy: Vertical Integration
  • 1.23.2 Broadcom's CPO Strategy: Open Ecosystem
  • 1.23.3 Competitive Dynamics
  • 1.23.4 CPO Product Benchmark: NVIDIA vs. Broadcom
  • 1.23.5 NVIDIA and Broadcom: Divergent CPO Ecosystems
• 1.24 Current AI System Architecture
  • 1.24.1 NVIDIA DGX/HGX Architecture
• 1.25 Future AI Architecture
• 1.26 Market Forecast
  • 1.26.1 Server Boards, CPUs, and GPUs/Accelerators
  • 1.26.2 Optical I/O for AI Interconnect CPO Forecast (Units Shipped)
  • 1.26.3 Optical I/O for AI Interconnect CPO Forecast (Revenue/Market Size)
  • 1.26.4 CPO Network Switches for AI Accelerators Forecast (Units Shipped)
  • 1.26.5 CPO Network Switches for AI Accelerators Forecast (Market Size and Revenue)
  • 1.26.6 Total CPO Market Overview
  • 1.26.7 Total CPO by Different EIC/PIC Integration Technology (Unit Shipments)
  • 1.26.8 System Integration of Network Switches by Packaging Technologies
  • 1.26.9 System Integration of Optical I/O Forecast by Packaging Technologies
• 1.27 Co-packaged optics (CPO) industrial ecosystem
  • 1.27.1 PIC Design Segment
  • 1.27.2 ASIC and xPU Design Segment
  • 1.27.3 Laser Sources Segment
  • 1.27.4 SOI Wafer and Epi-Wafer Segment
  • 1.27.5 EIC, Retimers, SerDes, and PHY Segment
  • 1.27.6 Connectors and Fibers Segment
  • 1.27.7 Foundries Segment
  • 1.27.8 Packaging, Assembling, and Testing Segment
  • 1.27.9 System and Equipment Segment
  • 1.27.10 End Customers (Hyperscalers) Segment
  • 1.27.11 Ecosystem Interdependencies and Strategic Implications

2 CHALLENGES AND SOLUTIONS FOR FUTURE AI SYSTEMS

• 2.1 The Rise and Challenges of Large Language Models (LLMs)
  • 2.1.1 The Explosive Growth of AI and Generative AI
    • 2.1.1.1 Historical Context and Acceleration
    • 2.1.1.2 Compute Demand Scaling
    • 2.1.1.3 Generative AI Market Expansion
  • 2.1.2 Modern High-Performance AI Data Centre Requirements
    • 2.1.2.1 Compute Density Requirements
    • 2.1.2.2 Network Topology Requirements
    • 2.1.2.3 Availability and Reliability Requirements
  • 2.1.3 NVIDIA's State-of-the-Art AI Systems
    • 2.1.3.1 DGX H100 and HGX H100
  • 2.1.4 Switches: Key Components in Modern Data Centres
    • 2.1.4.1 Switch Hierarchy in AI Data Centres
• 2.2 Scale-Up, Scale-Out, and Scale-Across Networks
  • 2.2.1 Scale-Up Networks: GPU-to-GPU Interconnects
    • 2.2.1.1 NVIDIA NVLink Implementation
    • 2.2.1.2 CPO Value Proposition for Scale-Up
  • 2.2.2 Scale-Out Networks: Rack-to-Rack Communications
    • 2.2.2.1 Ethernet-Based Scale-Out
    • 2.2.2.2 InfiniBand for AI
    • 2.2.2.3 CPO Value Proposition for Scale-Out
  • 2.2.3 Scale-Up, Scale-Out, and Scale-Across Comparison
• 2.3 Challenges in Network Switch Interconnects for High-End Data Centres
  • 2.3.1 Roadmap of Interconnect Technology for Network Switches in High-End Data Centres
    • 2.3.1.1 Technology Generations
  • 2.3.2 SerDes Bottleneck in High-Bandwidth Systems
    • 2.3.2.1 SerDes Function
    • 2.3.2.2 Channel Loss Challenges
  • 2.3.3 Solutions to SerDes Bottlenecks in High-Bandwidth Systems
    • 2.3.3.1 Linear-Drive Electronics
    • 2.3.3.2 Near-Package Optics
    • 2.3.3.3 Co-Packaged Optics
  • 2.3.4 Pluggable Optics: Current Bottlenecks and Limitations
    • 2.3.4.1 Form Factor Constraints
    • 2.3.4.2 Electrical Interface Limitations
    • 2.3.4.3 Thermal Management Challenges
    • 2.3.4.4 Serviceability Trade-offs
  • 2.3.5 On-Board Optics (OBO)
  • 2.3.6 Co-Packaged Optics (CPO)
    • 2.3.6.1 CPO Architecture
    • 2.3.6.2 Key Enabling Technologies
    • 2.3.6.3 Performance Benefits
    • 2.3.6.4 Implementation Challenges
  • 2.3.7 Transmission Losses in Pluggable Optical Transceiver Connections
    • 2.3.7.1 Total Path Loss
  • 2.3.8 Pluggable Optics vs. CPO
  • 2.3.9 Design Decisions for CPO Compared to Pluggables
  • 2.3.10 Advancements in Switch IC Bandwidth and the Need for CPO Technology
    • 2.3.10.1 Bandwidth Scaling Trajectory
    • 2.3.10.2 Physical Constraints at Scale
  • 2.3.11 L2 Frontside Network Architecture Diagram: CPO vs. Non-CPO
• 2.4 Challenges in Compute Switch Interconnects (Optical I/O) for High-End Data Centres
  • 2.4.1 Number of Copper Wires in Current AI System Interconnects
    • 2.4.1.1 NVLink Copper Cable Count
    • 2.4.1.2 SuperPOD Cable Complexity
  • 2.4.2 Limitations of Current Copper Systems in AI
  • 2.4.3 NVIDIA's Connectivity Choices: Copper vs. Optical for High-Bandwidth Systems
    • 2.4.3.1 Current Generation: Copper-Centric
    • 2.4.3.2 Transition Generation: Hybrid Approach
    • 2.4.3.3 Future Generation: Optical-First
    • 2.4.3.4 Strategic Implications
  • 2.4.4 Copper vs. Optical for High-Bandwidth Systems: Benchmark
  • 2.4.5 Migration from Copper to Optical Interconnects for High-End AI Systems
  • 2.4.6 Current AI System Architecture
  • 2.4.7 L1 Backside Compute Architecture with Copper Systems
  • 2.4.8 L1 Backside Compute Architecture with Optical Interconnect: Co-Packaged Optics (CPO)
  • 2.4.9 Opportunities for Swapping Copper to Optical
• 2.5 Future AI Systems in High-End Data Centres
  • 2.5.1 Power Efficiency Comparison: CPO vs. Pluggable Optics vs. Copper Interconnects
    • 2.5.1.1 Power Consumption Breakdown
  • 2.5.2 Latency of 60cm Data Transmission Technology Benchmark
  • 2.5.3 Future AI Architecture (Short to Mid-Term)
  • 2.5.4 Future AI Architecture (Long-Term)

3 INTRODUCTION TO CO-PACKAGED OPTICS (CPO)

• 3.1 Photonic Integrated Circuits (PICs) Key Concepts
  • 3.1.1 What are Photonic Integrated Circuits (PICs)?
    • 3.1.1.1 Fundamental Definition
    • 3.1.1.2 Material Platforms
    • 3.1.1.3 Integration Levels
  • 3.1.2 PICs vs. Silicon Photonics: What are the Differences?
    • 3.1.2.1 Silicon Photonics: A Specific Implementation
    • 3.1.2.2 Why Silicon Photonics Dominates CPO
  • 3.1.3 PIC Architecture
    • 3.1.3.1 Transmit Path Architecture
    • 3.1.3.2 Receive Path Architecture
    • 3.1.3.3 Supporting Functions
  • 3.1.4 Advantages and Challenges of PICs
• 3.2 Optical Engine (OE)
  • 3.2.1 What is an Optical Engine?
    • 3.2.1.1 Optical Engine Composition
    • 3.2.1.2 Optical Engine vs. Pluggable Transceiver
  • 3.2.2 How an Optical Engine Works
    • 3.2.2.1 Transmit Path Operation
    • 3.2.2.2 Receive Path Operation
    • 3.2.2.3 Critical Performance Parameters
  • 3.2.3 Optical Power Supplies
    • 3.2.3.1 Why External Laser Sources?
    • 3.2.3.2 External Laser Source Architectures
    • 3.2.3.3 Optical Power Delivery
• 3.3 Co-Packaged Optics
  • 3.3.1 Three Key Concepts in Co-Packaged Optics (CPO)
    • 3.3.1.1 Concept 1: Proximity Integration
    • 3.3.1.2 Concept 2: Functional Partitioning
    • 3.3.1.3 Concept 3: Coherent Ecosystem Development
  • 3.3.2 Key Technology Building Blocks for CPO
    • 3.3.2.1 Silicon Photonics PIC
    • 3.3.2.2 Electronic IC (EIC)
    • 3.3.2.3 EIC-PIC Integration
    • 3.3.2.4 Fibre Array Units (FAUs)
    • 3.3.2.5 External Laser Source
    • 3.3.2.6 Advanced Packaging Platform
  • 3.3.3 Benefits of CPO: Latency Reduction
    • 3.3.3.1 Sources of Latency in Optical Interconnects
    • 3.3.3.2 CPO Latency Advantages
  • 3.3.4 Benefits of CPO: Power Consumption Reduction
    • 3.3.4.1 Power Consumption Breakdown
    • 3.3.4.2 Why CPO Consumes Less Power
  • 3.3.5 Benefits of CPO: Data Rate Improvements
    • 3.3.5.1 Pluggable Scaling Limitations
    • 3.3.5.2 CPO Scaling Advantages
    • 3.3.5.3 Data Rate Scaling Roadmap
  • 3.3.6 Overview of Value Proposition of CPO
    • 3.3.6.1 Value for Hyperscale Data Centre Operators
    • 3.3.6.2 Value for Network Equipment Vendors
    • 3.3.6.3 Value for the Technology Ecosystem
  • 3.3.7 Future Challenges in CPO
    • 3.3.7.1 Manufacturing and Yield Challenges
    • 3.3.7.2 Thermal Management Challenges
    • 3.3.7.3 Serviceability and Reliability Challenges
    • 3.3.7.4 Ecosystem and Standardisation Challenges
    • 3.3.7.5 Cost Challenges
• 3.4 CPO Standards
  • 3.4.1 OIF Co-Packaging Framework
  • 3.4.2 OIF Standards for 1.6T and 3.2T CPO Module
  • 3.4.3 External Laser Small Form Pluggable (ELSFP) Implementation Agreement
  • 3.4.4 Telemetry and Management
  • 3.4.5 OIF's CEI-112G XSR / XSR+ PAM4
  • 3.4.6 UCIe Standard and Its Relationship to CPO
  • 3.4.7 The CPO Standards Process in China

4 PACKAGING FOR CO-PACKAGED OPTICS (CPO)

• 4.1 Introduction to CPO Packaging
  • 4.1.1 Key Components to be Packaged in an Optical Transceiver
    • 4.1.1.1 Photonic Integrated Circuit (PIC)
    • 4.1.1.2 Electronic Integrated Circuit (EIC)
    • 4.1.1.3 Laser Source Interface
    • 4.1.1.4 Fibre Array Unit (FAU)
    • 4.1.1.5 Host ASIC Interface
  • 4.1.2 Heterogeneous Integration and Co-Packaged Photonics
    • 4.1.2.1 Why Heterogeneous Integration for CPO?
    • 4.1.2.2 Heterogeneous Integration Approaches for CPO
    • 4.1.2.3 Integration Hierarchy for CPO
  • 4.1.3 CPO for Network Switch: Packaging Concept
    • 4.1.3.1 Switch Architecture with CPO
    • 4.1.3.2 Package Configuration Options
    • 4.1.3.3 Packaging Requirements for Switch CPO
  • 4.1.4 1.6 Tbps Co-Packaged Optics for Network Switch
    • 4.1.4.1 Integration Approach
  • 4.1.5 CPO as Optical I/O for XPUs: Packaging Concept
    • 4.1.5.1 The Scale-Up Interconnect Challenge
    • 4.1.5.2 XPU-CPO Packaging Concept
    • 4.1.5.3 Implementation Approaches
    • 4.1.5.4 NVIDIA's Approach to XPU Optical I/O
    • 4.1.5.5 Packaging Implications for XPU Optical I/O
    • 4.1.5.6 System Architecture Evolution
  • 4.1.6 CPO Integration for Compute Silicon
    • 4.1.6.1 System Configuration
    • 4.1.6.2 Integration Architecture
    • 4.1.6.3 Thermal Partitioning
    • 4.1.6.4 Enabled Architectures
  • 4.1.7 Overview of CPO Packaging Technologies
• 4.2 Overview and Development Roadmap of 2.5D and 3D Advanced Semiconductor Packaging Technologies
  • 4.2.1 Evolution Roadmap of Semiconductor Packaging
  • 4.2.2 Semiconductor Packaging Overview
  • 4.2.3 Key Metrics for Advanced Semiconductor Packaging Performance
  • 4.2.4 Overview of Interconnection Techniques in Semiconductor Packaging
  • 4.2.5 Overview of 2.5D Packaging Structure
  • 4.2.6 2.5D Package Components
  • 4.2.7 Benefits for CPO
  • 4.2.8 Challenges for CPO
• 4.3 2.5D Silicon-Based Packaging Technologies
  • 4.3.1 2.5D Packaging Involving Silicon as Interconnect
  • 4.3.2 Silicon Interposer Technology
  • 4.3.3 Silicon Bridge Technology
  • 4.3.4 CPO Implications
  • 4.3.5 Through-Silicon Via (TSV): Current State and Future
    • 4.3.5.1 TSV Fabrication Process
    • 4.3.5.2 TSV Technology Generations
    • 4.3.5.3 TSV Challenges for CPO
    • 4.3.5.4 Future TSV Development
  • 4.3.6 Development Trends for 2.5D Silicon-Based Packaging
    • 4.3.6.1 Interposer Size Scaling
    • 4.3.6.2 Routing Density Advancement
    • 4.3.6.3 Cost Reduction Initiatives
    • 4.3.6.4 Integration with Advanced Features
  • 4.3.7 Silicon Interposer vs. Silicon Bridge Benchmark
    • 4.3.7.1 Implications for CPO
• 4.4 2.5D Organic-Based Packaging Technologies
  • 4.4.1 2.5D Packaging: High-Density Fan-Out (FO) Packaging
    • 4.4.1.1 Fan-Out Technology Concept
    • 4.4.1.2 High-Density Fan-Out Variants
    • 4.4.1.3 Advantages for CPO
    • 4.4.1.4 Challenges for CPO
  • 4.4.2 Redistribution Layer (RDL)
    • 4.4.2.1 RDL Fabrication Process
    • 4.4.2.2 RDL Design Considerations for CPO
  • 4.4.3 Electronic Interconnects: SiO2 vs. Organic Dielectric
  • 4.4.4 Panel Level Fab-Out
    • 4.4.4.1 Panel-Level Processing
    • 4.4.4.2 Advantages for CPO
    • 4.4.4.3 Challenges for CPO
  • 4.4.5 Wafer Level Fan-Out
    • 4.4.5.1 Wafer-Level Processing
    • 4.4.5.2 Advantages for WLFO
    • 4.4.5.3 Challenges for WLFO
  • 4.4.6 Wafer-Level Fan-Out vs. Panel-Level Fan-Out
    • 4.4.6.1 Selection Criteria for CPO
  • 4.4.7 Key Trends in Fan-Out Packaging
  • 4.4.8 Challenges in Future Fan-Out Processes
    • 4.4.8.1 Die Shift and Placement Accuracy
    • 4.4.8.2 Warpage Control
    • 4.4.8.3 Yield and Cost
    • 4.4.8.4 High-Frequency Performance
• 4.5 2.5D Glass-Based Packaging Technologies
  • 4.5.1 Roles of Glass in Semiconductor Packaging
    • 4.5.1.1 Glass Properties Relevant to Packaging
    • 4.5.1.2 Applications in Packaging
    • 4.5.1.3 Glass Core as Interposer for Advanced Semiconductor Packaging
  • 4.5.2 Overcoming Limitations of Silicon Interposers with Glass
    • 4.5.2.1 Size Limitation
    • 4.5.2.2 Optical Opacity
    • 4.5.2.3 Dielectric Loss
    • 4.5.2.4 Cost Structure
    • 4.5.2.5 Remaining Silicon Advantages
  • 4.5.3 Glass vs. Molding Compound
    • 4.5.3.1 Implications for CPO
  • 4.5.4 Glass Core (Interposer) Package: Process Flow
  • 4.5.5 Challenges of Glass Packaging
    • 4.5.5.1 Handling and Breakage
    • 4.5.5.2 Via Formation and Metallisation
    • 4.5.5.3 Thermal Conductivity
    • 4.5.5.4 RDL Adhesion
    • 4.5.5.5 Warpage Control
• 4.6 3D Advanced Semiconductor Packaging Technologies
  • 4.6.1 Evolution of Bumping Technologies
    • 4.6.1.1 Solder Bumps (C4)
    • 4.6.1.2 Copper Pillar Bumps
    • 4.6.1.3 Micro-Bumps
    • 4.6.1.4 Hybrid Bonding (Bumpless)
  • 4.6.2 Challenges in Scaling Bumps
    • 4.6.2.1 Mechanical Challenges
    • 4.6.2.2 Electrical Challenges
    • 4.6.2.3 Manufacturing Challenges
    • 4.6.2.4 Implications for CPO
  • 4.6.3 Micro-Bump for Advanced Semiconductor Packaging
    • 4.6.3.1 Micro-Bump Structure
  • 4.6.4 Bumpless Cu-Cu Hybrid Bonding
    • 4.6.4.1 Hybrid Bonding Concept
    • 4.6.4.2 Process Fundamentals
    • 4.6.4.3 Key Characteristics
    • 4.6.4.4 Benefits for CPO
  • 4.6.5 Three Ways of Cu-Cu Hybrid Bonding: Benchmark
    • 4.6.5.1 Die-to-Die (D2D)
    • 4.6.5.2 Die-to-Wafer (D2W)
    • 4.6.5.3 Wafer-to-Wafer (W2W)
  • 4.6.6 Challenges in Cu-Cu Hybrid Bonding Manufacturing Process
• 4.7 CPO Packaging: EIC and PIC Integration
  • 4.7.1 EIC/PIC Integration by Conventional Interconnect Techniques
    • 4.7.1.1 Wire Bond Integration
    • 4.7.1.2 Flip-Chip Integration (2D)
  • 4.7.2 EIC/PIC Integration by Emerging Interconnect Techniques
    • 4.7.2.1 2.5D Interposer Integration
    • 4.7.2.2 3D Micro-Bump Stacking
    • 4.7.2.3 3D Hybrid Bonding
  • 4.7.3 2D to 3D EIC/PIC Integration Options
    • 4.7.3.1 Technology Transition Drivers
    • 4.7.3.2 2D to 3D Integration Evolution
  • 4.7.4 Integration Roadmap by CPO Segment
  • 4.7.5 Benchmarking of Different Packaging Technologies for EIC/PIC
  • 4.7.6 Pros and Cons of 2D Integration of EIC/PIC
  • 4.7.7 Pros and Cons of 2.5D Integration of EIC/PIC
  • 4.7.8 Pros and Cons of 3D Hybrid Integration of EIC/PIC
  • 4.7.9 Pros and Cons of 3D Monolithic Integration of EIC/PIC
• 4.8 TSV for EIC/PIC Integration
  • 4.8.1 TSV for EIC/PIC Integration in CPO
    • 4.8.1.1 TSV Configurations for EIC/PIC
    • 4.8.1.2 Design Considerations
  • 4.8.2 Benefits of TSV for PIC/EIC Integration
  • 4.8.3 Cisco Packaging Architectures of Optical Engine Over Generations
  • 4.8.4 Cisco: 2.5D Chip-on-Chip (CoC) Packaging Architecture for EIC/PIC Integration
    • 4.8.4.1 Architecture Description
    • 4.8.4.2 Manufacturing Considerations
  • 4.8.5 Cisco: 3D TSV for PIC/EIC Integration
    • 4.8.5.1 Architecture Description
    • 4.8.5.2 Benefits of TSV Integration
    • 4.8.5.3 Manufacturing Considerations
  • 4.8.6 Key TSV Fabrication Steps and Challenges in CPO
    • 4.8.6.1 Fabrication Process Flow
  • 4.8.7 Packaging Options for Silicon Photonics
  • 4.8.8 Pros and Cons of 2.5D Si Interposer for EIC/PIC Integration
• 4.9 Fan-Out for EIC/PIC Integration
  • 4.9.1 ASE's Proposed Fan-Out Solution for CPO Packaging
    • 4.9.1.1 ASE Fan-Out CPO Concept
  • 4.9.2 FOPOP from ASE: Process
  • 4.9.3 Analysis of FOPOP vs. Wire Bond Packaging for CPO
  • 4.9.4 Optical Packaging Process Considerations for Silicon Photonics - ASE
  • 4.9.5 SPIL's Fan-Out Embedded Bridge (FOEB) Structure for PIC/EIC Integration in CPO
  • 4.9.6 Process Flow of Integrating PIC and EIC in a FOEB Structure
  • 4.9.7 Process Challenges in Packaging Optical Engines
  • 4.9.8 Challenges of Using Fan-Out for EIC/PIC Integration
• 4.10 Glass-Based CPO Packaging Technologies
  • 4.10.1 Glass-Based Co-Packaged Optics
    • 4.10.1.1 Corning's Glass CPO Vision
  • 4.10.2 Glass CPO Package Architecture
  • 4.10.3 Glass-Based CPO Process Development
    • 4.10.3.1 Corning's 102.4 Tb/s Test Vehicle Demonstration
  • 4.10.4 3D Heterogeneous Integration of EIC/PIC on a Glass Interposer
    • 4.10.4.1 Architecture Rationale
    • 4.10.4.2 Package Architecture
    • 4.10.4.3 Process Flow
    • 4.10.4.4 Representative Switch Module Example
    • 4.10.4.5 Market Trajectory
• 4.11 Hybrid Bonding for EIC/PIC Integration
  • 4.11.1 TSMC: Integrated HPC Technology Platform for AI
  • 4.11.2 iOIS: Integrated Optical Interconnection System from TSMC
  • 4.11.3 Combining EIC and PIC with 3D SoIC Bond
  • 4.11.4 Roadmap of Bond Pitch Scaling
• 4.12 System Integration of Optical Engine and ASIC/XPU
  • 4.12.1 Co-Packaging vs. Co-Packaged Optics (CPO)
  • 4.12.2 Three Types of CPO + XPU/Switch ASIC Packaging Structures
    • 4.12.2.1 Type 1: 2D/2.5D Peripheral Integration
    • 4.12.2.2 Type 2: 2.5D with Embedded Bridge
    • 4.12.2.3 Type 3: 3D Stacked Integration
• 4.13 Future 3D-CPO Structure
  • 4.13.1 Future 3D-CPO Architecture Vision
  • 4.13.2 NVIDIA's 3D Integration of SoC, HBM, EIC, and PIC on Co-Packaged Substrates
    • 4.13.2.1.1 Architecture Overview
    • 4.13.2.1.2 Integration Approach
    • 4.13.2.1.3 Key Innovations
• 4.14 Optical Alignment and Laser Integration
  • 4.14.1 How CPO is Built and the Bottleneck
  • 4.14.2 The fibre attach bottleneck
  • 4.14.3 Interface Between Coupler and FAU
  • 4.14.4 Grating vs. Edge Couplers: Challenges in High-Density Optical I/O for Silicon Photonics
  • 4.14.5 Challenges in High-Density Optical I/O for Silicon Photonics
• 4.15 Fiber Array Unit (FAU)
  • 4.15.1 Optical Alignment Challenges and Solutions
  • 4.15.2 Two Alignment Approaches
  • 4.15.3 Reducing Optical Fiber Packaging Complexity
  • 4.15.4 Key Technical Challenges
    • 4.15.4.1 The Size Mismatch Between Silicon Waveguides and Planar Optical Fibers
  • 4.15.5 Fiber Attach Methods
  • 4.15.6 Key Players in FAU for CPO
  • 4.15.7 Benchmark of Optical Fiber Alignment Structure Variations
  • 4.15.8 Suppliers of Other Optical Components in CPO
• 4.16 Suppliers of Other Optical Components in CPO
• 4.17 Laser Integration
  • 4.17.1 On-Chip Light Source Integration Methods
  • 4.17.2 External Lasers for CPO
  • 4.17.3 Laser Attach Technology Benchmark
  • 4.17.4 Benchmark of Different Laser Integration Technologies

5 CO-PACKAGED OPTICS MARKET ANALYSIS

• 5.1 CPO Market Definition and Scope
• 5.2 CPO Market Size and Growth Projections
• 5.3 Switch CPO Market Analysis
  • 5.3.1 Market Overview and Drivers
  • 5.3.2 Deployment Timeline and Adoption Phases
  • 5.3.3 Volume Projections and Market Sizing
  • 5.3.4 Market Concentration and Regional Distribution
  • 5.3.5 Pricing Trajectory and Cost Dynamics
• 5.4 XPU Optical I/O Market Analysis
  • 5.4.1 Market Drivers and Value Proposition
  • 5.4.2 Adoption Timeline and Platform Evolution
  • 5.4.3 Volume and Revenue Projections
  • 5.4.4 Market Segmentation by Platform
  • 5.4.5 Technology Requirements and Differentiation
• 5.5 CPO Pricing and Cost Analysis
  • 5.5.1 Current Pricing Landscape
  • 5.5.2 Cost Trajectory and Reduction Drivers
  • 5.5.3 Cost Parity Timeline and Dynamics
  • 5.5.4 Pricing Strategy Implications
• 5.6 Regional Market Dynamics
  • 5.6.1 North America
  • 5.6.2 Asia-Pacific
  • 5.6.3 Europe
  • 5.6.4 Rest of World
• 5.7 Total Addressable Market Analysis
  • 5.7.1 Core TAM Segments
  • 5.7.2 Serviceable Addressable Market (SAM)
• 5.8 Market Forecast by Component
• 5.9 Market Forecast by Technology Generation
  • 5.9.1 Optical Engine Bandwidth Evolution
  • 5.9.2 Generation Lifecycle Analysis
• 5.10 Market Restraints and Barriers
  • 5.10.1 Manufacturing Yield and Cost
  • 5.10.2 Serviceability and Field Replacement Concerns
  • 5.10.3 Standards Maturity and Interoperability
  • 5.10.4 Supply Chain Capacity Constraints
  • 5.10.5 Competitive Alternatives
• 5.11 Adoption Curve Analysis
  • 5.11.1 Technology Adoption Framework
    • 5.11.1.1 Innovators (2024-2026)
    • 5.11.1.2 Early Adopters (2026-2028)
    • 5.11.1.3 Early Majority (2028-2031)
    • 5.11.1.4 Late Majority (2031-2034)
    • 5.11.1.5 Laggards (2034+)
  • 5.11.2 Segment-Specific Adoption Curves
• 5.12 Adoption Accelerators and Inhibitors
  • 5.12.1 Adoption Curve Implications
• 5.13 Competitive Landscape Evolution
  • 5.13.1 Current Competitive Positioning
  • 5.13.2 Integrated Device Manufacturers (IDMs)
  • 5.13.3 Silicon Photonics Specialists
  • 5.13.4 Foundry/OSAT Providers
  • 5.13.5 System Vendors
  • 5.13.6 Laser Suppliers
  • 5.13.7 Competitive Dynamics and Market Structure Evolution
    • 5.13.7.1 Near-Term Dynamics (2025-2028)
      • 5.13.7.1.1 Expected Evolution (2028)
    • 5.13.7.2 Mid-Term Dynamics (2028-2032)
      • 5.13.7.2.1 Expected Evolution (2032)
    • 5.13.7.3 Long-Term Dynamics (2032-2036)
      • 5.13.7.3.1 Expected Evolution (2036)
  • 5.13.8 Vertical Integration Trends
    • 5.13.8.1 Integration Strategy Framework
      • 5.13.8.1.1 Full Vertical Integration (Broadcom, Intel Model)
      • 5.13.8.1.2 Partial Integration (Cisco, NVIDIA Model)
      • 5.13.8.1.3 Fabless/Assembly-Light (Ayar Labs, Ranovus Model)
      • 5.13.8.1.4 Platform Provider (TSMC Model)
    • 5.13.8.2 Strategic Implications of Integration Trends
  • 5.13.9 Recent Developments — Q1 2026 Update
• 5.14 Scenario Analysis
  • 5.14.1 Scenario Framework
  • 5.14.2 Scenario Definitions
  • 5.14.3 Bull Case Scenario
  • 5.14.4 Base Case Scenario
  • 5.14.5 Bear Case Scenario
  • 5.14.6 Scenario Comparison and Key Variables

6 GLOBAL MARKET TRENDS IN DATACOM

• 6.1 Introduction to DATACOM Market Dynamics
  • 6.1.1 Overview of the Data Communications Market
    • 6.1.1.1 Market Definition and Scope
    • 6.1.1.2 Market Size and Growth
  • 6.1.2 Key Market Drivers
    • 6.1.2.1 Artificial Intelligence and Machine Learning
    • 6.1.2.2 Cloud Computing Growth
    • 6.1.2.3 Data Growth
    • 6.1.2.4 Power and Sustainability Pressures
• 6.2 Application Trends
  • 6.2.1 AI and Machine Learning Workload Growth
    • 6.2.1.1 The AI Training Revolution
    • 6.2.1.2 Training Cluster Architecture Evolution
    • 6.2.1.3 AI Inference Deployment
    • 6.2.1.4 Market Quantification
    • 6.2.1.5 Implications for CPO
  • 6.2.2 Hyperscale Data Centre Expansion
    • 6.2.2.1 Defining Hyperscale
  • 6.2.3 Global Hyperscale Capacity
  • 6.2.4 Regional Distribution
  • 6.2.5 Hyperscaler Investment Trends
    • 6.2.5.1 Capital expenditure acceleration
    • 6.2.5.2 AI-Specific Infrastructure
    • 6.2.5.3 Implications for CPO
  • 6.2.6 Edge Computing and Distributed AI
    • 6.2.6.1 Market Growth
  • 6.2.7 Edge AI Applications
  • 6.2.8 Edge Network Architecture
• 6.3 Technology Trends
  • 6.3.1 Technology Trends Overview
    • 6.3.1.1 Key Technology Vectors
    • 6.3.1.2 Technology Interdependencies
  • 6.3.2 Technology Trends: Packaging
  • 6.3.3 Universal Chiplet Interconnect Express (UCIe)
  • 6.3.4 Laser Sources for CPO
  • 6.3.5 External vs. Integrated Laser

7 MARKET OUTLOOK

• 7.1 Hybrid Pluggable-to-CPO Transition, 2026–2030
• 7.2 Scale-Out Outlook
  • 7.2.1 Scale-Out CPO Market Evolution
    • 7.2.1.1 Scale-Out Market Drivers
    • 7.2.1.2 Market Evolution Phases
    • 7.2.1.3 Scale-Out CPO Market Forecast
  • 7.2.2 Scale-Out Technology Roadmap
    • 7.2.2.1 Technology Generation Evolution
    • 7.2.2.2 Technology Enablers by Generation
  • 7.2.3 Scale-Out Key Players and Competitive Landscape
• 7.3 Scale-Up Outlook
  • 7.3.1 Scale-Up CPO Market Evolution
  • 7.3.2 Copper to Optical Transition
  • 7.3.3 Optical I/O Solution
  • 7.3.4 Scale-Up CPO Market Forecast
  • 7.3.5 Market Evolution Phases
  • 7.3.6 Scale-Up Technology Roadmap
    • 7.3.6.1 NVIDIA Optical I/O Evolution
    • 7.3.6.2 AMD Optical I/O Evolution
    • 7.3.6.3 Custom Silicon Optical I/O
  • 7.3.7 Scale-Up Key Players and Competitive Landscape
    • 7.3.7.1 Competitive Landscape Overview
• 7.4 High-Density Connectors
  • 7.4.1 High-Density Connectors vs. CPO
    • 7.4.1.1 Scenario 1: Connectors Enable Extended Pluggable (Low CPO Impact)
    • 7.4.1.2 Scenario 2: Connectors Complement CPO (Moderate Impact)
    • 7.4.1.3 Scenario 3: Connectors Enable "Near-Packaged" Optics (Moderate CPO Impact)
    • 7.4.1.4 Scenario 4: Connector Development Delays (Positive CPO Impact)
• 7.5 Emerging Supply Chain Dynamics
  • 7.5.1 Geographic Concentration in CPO Supply Chains
• 7.6 Third-Party Suppliers and Systems Integrators
  • 7.6.1 Multi-Tier Supply Chain Architecture
    • 7.6.1.1 Tier 1: Silicon Photonics Platform
    • 7.6.1.2 Tier 2: CPO Assembly (OSAT)
    • 7.6.1.3 Tier 3: Fiber Array Unit (FAU) Suppliers
    • 7.6.1.4 Tier 4: External Laser Source (ELS) Suppliers
    • 7.6.1.5 Tier 5: Optical Fiber Supply
    • 7.6.1.6 Tier 6: Optical Sub-Assembly Integration
  • 7.6.2 Strategic Implications for Supply Chain Participants

8 COMPANY PROFILES 367 (63 company profiles)

9 APPENDIX

• 9.1 Research Methodology and Data Sources

10 REFERENCES